Tatsuya Kaneko

Tatsuya Kaneko

Project Assistant Professor

The University of Tokyo

Biography

Tatsuya Kaneko is currently a Project Assistant Professor with the Graduate School of Information Science and Technology, The University of Tokyo, Tokyo, Japan. His research interests include algorithm and hardware architecture for machine learning and federated learning.

Interests
  • Machine Learning
  • Edge-AI
  • Hardware/ Software Co-design
  • On-device Training
  • Federated Learning
Education

  • Ph.D. in Engineering, 2023

    Hokkaido University

  • M.E., 2020

    Hokkaido University

  • B.E., 2018

    Hokkaido University

Experience

 
 
 
 
 
Project Assistant Professor
The University of Tokyo,
April 2023 – Present
Takamaeda Laboratory, Department of Computer Science, Graduate School of Information Science and Technology, The University of Tokyo
 
 
 
 
 
JSPS Research Fellow (DC2)
April 2021 – March 2023

Recent Publications

エッジAIのオンライン学習に向けた学習アルゴリズムの軽量化
金子 竜也, 百瀬 啓, 浅井 哲也
Cite
On-Device Training Architecture for Analog ReRAM Neural Networks with Digital BP
Tatsuya Kaneko, Hiroshi Momose, Tetsuya Asai
Cite
エッジAIのオンライン学習に向けたハードウェア指向対数量子化オプティマイザの提案
金子 竜也, 山岸 善治, 百瀬 啓, 浅井 哲也
Cite
Holmes: A hardware-oriented optimizer using logarithms
Y. Yamagishi, T. Kaneko, M. Akai-Kasaya, T. Asai
Cite
最適化装置及び最適化方法並びに最適化用プログラム
浅井哲也, 山岸善治, 金子竜也
Cite
See all publications

Awards

令和4年度北海道大学大学院情報科学院 - 学院長賞（博士）
北海道大学 Mar 2023
2019年度非線形問題研究会発表奨励賞
電子情報通信学会 非線形問題研究会 May 2020
エッジAIに向けた三値バックプロパゲーション法とそのFPGA実装,
令和4年度北海道大学大学院情報科学院 - 学院長賞（修士）
北海道大学 Mar 2020
MAKER OF MERIT 2019
Maker Faire Rome Oct 2019
Reconfigurable AI shield for embedded microcontrollers,
NCSP19 Student Paper Award
The Research Institute of Signal Processing Mar 2019
Hardware-oriented algorithm and architecture for generative adversarial networks,

Contact